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Walking through your layout database, Part 2

In part 1 (which you can read here) I described the benefits of visually inspecting the layout database for signal integrity problems. In that true story a large SI team had run a fancy SI analysis tool on the database for their very complex circuit board and had found nothing amiss.

However, a quick walkthrough uncovered two pages of things needing further investigation. The following from that list were fatal.

  1. Serpentine trace used to add delay in a memory system was improperly designed and had crosstalk excessive enough to cause ‘laddering’. The SI CAD tool noticed the serpentine and faithfully added the delays from each segment to come up with a total, but it didn’t account for the way in which crosstalk would have reduced the total delay. In fact, it proudly reported the (incorrect) delay to 3 decimal places!
  2. The SI tool didn’t report that dcaps were sharing vias with other devices (in one case a clock driver). This had a huge potential to create data dependent switching noise that could wreak havoc with the clock system.
  3. Terminating resistors for a very wide memory bus picked up Vtt (the termination voltage) from a very small island carved out of a power plane deep within the stackup. The voltage regulator feeding it was located a distance away, and was connected by a wide microstrip and a few vias. Because the island was deep in the stackup the long visas necessary to connect the regulator (and the dcap) to the island, and the long vias necessary to connect the resistors to Vtt were very inductive. A better solution (which was eventually implemented on a later spin of the board) was to move the island to the surface on the same side of the board where the termination resistors were located. This eliminated all of the vias and significantly improved signal quality. The SI tool had no understanding of this: it was happy because the voltage regulator was connected to a Vtt node, to which the termination resistors were connected.
  4. High-speed diff-pairs were run very near holes in the circuit board where screws attached the board   to a carrier. In some cases the diff-pairs ran alongside a series of these holes, but in one astonishing case a diff-pair was split such that one hole was placed in between the two traces forming the diff pair. A sketch of this type of problem appears in Figure 13.13 of “Understanding Signal Integrity” (but that diagram shows the discontinuity as a via and antipad rather than a bolt hole).
  5. The final one was perhaps the most subtle. A very wide high-speed memory bus was run as dual stripline. The layout designer had properly kept all the memory signals on the lower layer of the dual stripline, and had routed slow speed miscellaneous signals (including reset) on the upper dual stripline layer. This would have been fine provided those signals were not routed the same direction as the signals in the lower layer. Here is where multiple errors simultaneously came together to break the design. The first mistake was when the SI engineer specified that the reset signal was to be kept “as short as possible” (an instruction often given to layout designers but which really has no meaning). Faithfully following orders, the layout designer ran the reset trace diagonally across the board (it ended up as 18 inches [46cm]), since this gave a shorter length than a Manhattan route (nearly 30 inches [75cm]). That was the second mistake since the routing caused the trace to cut across (and so, pick up coupling from) every signal in the memory system and many other signals as well. Which leads us to mistake three: The SI engineer ran a simple TLINE simulation using the 18 inches from the length report which showed that the termination he had selected was adequate. Unfortunately his simulation didn’t include coupling from the other signals and so ignored crosstalk. The SI tool didn’t pick up on this because it was told to only analyze the memory subsystem. Since the coupling from the reset signal to each individual memory trace was small, it didn’t raise a flag. However, the total coupling from all of the memory traces TO the reset signal was very high. High enough in fact to cause reset to glitch when many of the memory traces simultaneously changed state in the same direction. Here the SI engineer was blinded by the impressive looking report generated by the tool.

The moral: always verify the cad tool results. Don’t just blindly accept the results and assume the tool is doing what you actually want.

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