Thierauf Design & Consulting: Signal Integrity Design, Analysis & Training

The 2ed edition of High-Speed Circuit Board Signal Integrity is now available!

You can get it directly from the publisher. Click here if you're in North America. Or click here if you are in Europe or Asia.

It should be available from Amazon and other book sellers shortly.

thierauf lab manual coverA sample chapter from Introduction to Signal Integrity: A Laboratory Manual is available.

Click here to download the PDF (you must be able to read PDFs in Version 9 or later). The file contains the Table of Contents, the entire Preface and part of Chapter 5 (but some graphics and text have been removed). Note that the print quality of the actual manual is much better than that presented in the sample chapter.

To order your copy, click here.

 

 

 

Table of Contents

Preface
Chapter 1 Signal Integrity Background Material
Chapter 2 Transmission Line Fundamentals
Chapter 3 Laboratory Exercises: Impedance and Delay
Chapter 4 Overview of Reflections and Terminations
Chapter 5 Laboratory Exercises: Reflections and Terminations
Chapter 6 Fundamentals of Crosstalk
Chapter 7 Laboratory Exercises: Measuring Crosstalk
Appendix A. Test Setup Build Notes
Appendix B. Selecting and Preparing the Cable
Appendix C. Oscilloscope Probing Techniques
Bibliography

In a previous blog I mentioned how the lossy transmission line model included in some versions of SPICE won’t properly simulate pulses. There’s been a lot of interest in this since that posting went live, especially with regards to finding the conductance loss and in using lossy TLINES in the free or reduced cost SPICE simulators.

Some SPICE based circuit simulators include the LTRA (Lossy TRAnsmission line) model (the “O” element). It simulates TLINE behavior (including loss) for one signal conductor at one frequency. That’s why it works well for single frequency waves (such as low distortion sine waves), but it doesn’t properly calculate losses for pulses, which are made of many frequencies (harmonics). And, since the “O” line only models one signal, it can’t be used to determine crosstalk or to simulate differential pairs.

With these caveats in mind, here’s how to calculate the parameters for a 50 ohm, 5-mil wide, half-ounce thick stripline on FR4. Some of you may recognize the raw data as coming from problem 7.12 of “Understanding Signal Integrity”.

The model requires we know the trace length (LEN), along with its capacitance (C), inductance (L), resistance (R), and conductance (G) all determined at the frequency of interest. The resistance models signal loss of the conductor metal, and the conductance models the dielectric loss. Both of these get larger as frequency increases, but the model uses the same values for all frequencies.

We’ll use 350MHz (the same frequency used in problem 7.12). R, L and C are found at that frequency with a field solver, or by using the graphs or formulas in the book, to be (per inch length):

C = 3.5p

L=8.7n

R=0.7

We recall from the text that R is the AC resistance of the trace and its return path at 350MHz. It’s not the DC value.

All we need to do now is to calculate G to complete the model. As I show in the text and in problem 7.11, this is easily done once we know the capacitance and the circuit boards loss tangent (which we’ll take to be 0.02 for FR4).

G = 6.28 x f x C x LT = 6.28 x 350MHz x 3.5pF x 0.02 = 154uS/inch

The loss is given in Siemens per unit length (using the same units as for the capacitance). For a 15 inch long line at 350MHz the final model becomes:

.MODEL LOSSY50SL LTRA

+C=3.5p

+L=8.7n

+R=0.7

+G=154u

+LEN=15

As I show in the book, these need to be scaled when using the “W” line model. But that’s for another post.

One of the most common capacitor related questions I get from clients and readers regards the way ceramic capacitors are classified.

As I've noted elsewhere, Class II ceramic dielectrics (which are used to create most ceramic decoupling capacitors, such as X7R types) are made with materials that cause the capacitance to change with temperature and bias voltage. A three character identification scheme is used to describe these effects: The 1st and 2ed characters indicate the temperature span, and the 3ed shows by how much the capacitance can change over that range. For instance, the capacitance of the popular X7R type capacitor can change by +/- 15% (indicated by the "R") when operating from -55C (indicated by the "X") to +125C (indicated by the "7"). This change is in addition to the tolerance of the capacitor, which is measured at 25C (or sometimes 20C) and low bias voltage. Operating an X7R at 50% of its working voltage rating can result in the capacitance being reduced by nearly 20%, while the capacitance can be reduced by as much as 80% for other Class II dielectrics. The identification code doesn't directly show the way voltage changes the capacitance, but in general the "X" series is the least affected, followed by the "Y" and then the "Z" series. Manufacturer's literature sometimes shows this, and it's described in detail in chapter 10 of High-Speed Circuit Board Signal Integrity. Incidentally, a Class I dielectric (such as a C0G) should be used in those situations where the capacitance must not change with bias, such as integrators, PLL's and timing circuits.

Here's what each of the most common character codes mean for Class II dielectrics (Class I dielectrics such as C0G have their own, very different, code):

X = -55C              5 = +85C              R = +/- 15%

Y = -30C               6 = +105C            U = +22%, - 56%

Z = +10C               7 = +125C           V = +22%, -82%

 

One more note on Class II ceramic capacitors: remember the capacitance falls as they age, even when the circuit is not powered up. The "X" series show the least amount of aging (typically under 2.5% per decade hour), while the "Z" series the most (as much as 7% in reduction of capacitance per decade hour). But that's for another post.

If you need a 3-D field solver, you might want to give Simbeor (http://www.simberian.com/) a try. This year it again won the Design Con Design Vision Award (it was the 2010 winner, too).

A big plus for me is that Simbeor results have been verified against measurement of actual hardware (you can get details on this from the Siberian website).

Some 3-D solvers can be very difficult to properly use, especially if you don't build models with them daily. The special tricks required to correctly assign ports or to set boundary conditions are easy to forget unless you use the tool enough to become truly expert.

In contrast, I've found it easy to build 3D transmission line and via models in Simbeor, even when I haven't used it for a while. The tutorials are excellent, and the website has a very nice collection of technically useful white papers (several of which I reference in "Understanding Signal Integrity").

This is a great tool for designing serial channels, designing vias, and analyzing the electrical behavior of interconnect (including, but not only, very high-performance interconnect). The website is worth checking out: It's a good resource for those wishing to learn about the electrical characteristics of high-performance serial signaling.

In part 1 (which you can read here) I described the benefits of visually inspecting the layout database for signal integrity problems. In that true story a large SI team had run a fancy SI analysis tool on the database for their very complex circuit board and had found nothing amiss.

However, a quick walkthrough uncovered two pages of things needing further investigation. The following from that list were fatal.

  1. Serpentine trace used to add delay in a memory system was improperly designed and had crosstalk excessive enough to cause ‘laddering’. The SI CAD tool noticed the serpentine and faithfully added the delays from each segment to come up with a total, but it didn’t account for the way in which crosstalk would have reduced the total delay. In fact, it proudly reported the (incorrect) delay to 3 decimal places!
  2. The SI tool didn’t report that dcaps were sharing vias with other devices (in one case a clock driver). This had a huge potential to create data dependent switching noise that could wreak havoc with the clock system.
  3. Terminating resistors for a very wide memory bus picked up Vtt (the termination voltage) from a very small island carved out of a power plane deep within the stackup. The voltage regulator feeding it was located a distance away, and was connected by a wide microstrip and a few vias. Because the island was deep in the stackup the long visas necessary to connect the regulator (and the dcap) to the island, and the long vias necessary to connect the resistors to Vtt were very inductive. A better solution (which was eventually implemented on a later spin of the board) was to move the island to the surface on the same side of the board where the termination resistors were located. This eliminated all of the vias and significantly improved signal quality. The SI tool had no understanding of this: it was happy because the voltage regulator was connected to a Vtt node, to which the termination resistors were connected.
  4. High-speed diff-pairs were run very near holes in the circuit board where screws attached the board   to a carrier. In some cases the diff-pairs ran alongside a series of these holes, but in one astonishing case a diff-pair was split such that one hole was placed in between the two traces forming the diff pair. A sketch of this type of problem appears in Figure 13.13 of “Understanding Signal Integrity” (but that diagram shows the discontinuity as a via and antipad rather than a bolt hole).
  5. The final one was perhaps the most subtle. A very wide high-speed memory bus was run as dual stripline. The layout designer had properly kept all the memory signals on the lower layer of the dual stripline, and had routed slow speed miscellaneous signals (including reset) on the upper dual stripline layer. This would have been fine provided those signals were not routed the same direction as the signals in the lower layer. Here is where multiple errors simultaneously came together to break the design. The first mistake was when the SI engineer specified that the reset signal was to be kept “as short as possible” (an instruction often given to layout designers but which really has no meaning). Faithfully following orders, the layout designer ran the reset trace diagonally across the board (it ended up as 18 inches [46cm]), since this gave a shorter length than a Manhattan route (nearly 30 inches [75cm]). That was the second mistake since the routing caused the trace to cut across (and so, pick up coupling from) every signal in the memory system and many other signals as well. Which leads us to mistake three: The SI engineer ran a simple TLINE simulation using the 18 inches from the length report which showed that the termination he had selected was adequate. Unfortunately his simulation didn’t include coupling from the other signals and so ignored crosstalk. The SI tool didn’t pick up on this because it was told to only analyze the memory subsystem. Since the coupling from the reset signal to each individual memory trace was small, it didn’t raise a flag. However, the total coupling from all of the memory traces TO the reset signal was very high. High enough in fact to cause reset to glitch when many of the memory traces simultaneously changed state in the same direction. Here the SI engineer was blinded by the impressive looking report generated by the tool.

The moral: always verify the cad tool results. Don’t just blindly accept the results and assume the tool is doing what you actually want.

If you are looking for a version of SPICE to perform some basic circuit analysis, including elementary signal integrity analysis, you might consider using one of the free versions provided by the various major semiconductor vendors.

As I describe at the end of this note, just be careful how you use the transmission line models, and you’re limited in the types of I/O models you’ll be able to simulate because these simulators don’t support IBIS or encrypted transistor models. You’ll need to use a “full blown” version of SPICE to perform professional quality SI simulations.

Arguably the best known of the free Windows versions of SPICE is LTSPICE, which Linear Technology has made available for some time now. LTSPICE IV can be downloaded from the Linear Tech website here:

http://www.linear.com/designtools/software/gclid=CNaN2ZmwwqcCFYHc4AodAjnhAg#LTspice

The download includes models for a large selection of LTs product line, but models for a nice collection of transistors and diodes often used in switching power supply applications are also included. Models for other devices (such as transistors or diodes not included in the original library) can be easily added by the user.

Texas Instruments offers TINA (from Design Soft). It, too, is free and runs under Windows. It can be down loaded from the TI website:

http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html

TINA includes models of many TI analog components, and also for various transistors and diodes. Macro models for a number of logic devices and some analog components are provided, too. For instance, they have a macro for the 555 timer.

Analog Devices has just announced a new version of National Instruments Multisim for the evaluation of ADI’s components. The download is free, runs under Windows, but is limited to 50 components. The download license agreement precludes student use. Download the ADI version of Multisim from the ADI site:

https://lumen.ni.com/nicif/us/evalmultisimadi/content.xhtml

This version of Multisim includes models for many components in ADI’s portfolio, and some transistors and diodes, too.

LTSPICE and Multisim include single conductor lossless and single frequency lossy transmission line models. These TLINES are useful in predicting the severity of reflections, and the effects of terminations. However, since the TLINEs are single conductor, crosstalk can’t be measured, but because the model includes the TLINE reference terminals, coupling over a noisy ground plane can be simulated.

The lossy TLINES include series resistance and (shunt) conductance terms, which are used to account for conductor and dielectric losses. But, because the values don’t change with frequency, these lossy TLINEs are only good for modeling losses at the one specific frequency for which the resistance and conductance are valid. So you shouldn’t expect these TLINEs to properly account for losses in pulse circuits, but they give good results when a single frequency sinusoid is transmitted.

Now that you’ve picked the values for your ceramic decoupling capacitors, how do you decide on the working voltage rating? This is an important factor because unless you derate the dcap working voltage there’ll be less capacitance in the design than you had intended.

It turns out that the actual capacitance value of class II ceramic capacitors such as a 0.1uF X7R or Y5V dcap is influenced by the intensity of the electric field within the capacitor. Class II is the ceramic class from which almost all capacitors used for decoupling on commercial printed circuit boards comes from. Even when the power supply voltage in a circuit is low, the small size of modern SMT capacitors means the electric fields within the dcap can be quite high. And, the fields will be even higher in those capacitors constructed of many plates which are separated by a thin smear of dielectric (this is one of the techniques used by vendors get high values of capacitance in such small packages).

I’ve written extensively on the makeup and characteristics of Class I and Class II ceramic capacitors, but manufacturer’s datasheets and websites also have lots of great information. Some vendors offer software that you can use showing how their capacitors are affected by temperature and voltage. One of my favorites is SpiCap3.0 from AVX, which you can check out here.

If you drill into this you’ll see how strongly the capacitance of class II ceramic capacitors is reduced by voltage. The best way is to look at this is to plot the capacitance as a percentage of the specified working voltage. For instance, you’ll find that, depending on the body style, capacitance value and manufacturer, when exposed to voltages of 50% or more of the working voltage rating, the capacitance of an X7R can be reduced by as much as 20% over its datasheet value. The capacitance can be as low as an astonishing 20% of the specified value for an Y5V, and can be close to that for a Z5U.

The amount of capacitance and the body style determine the number and thickness of the plates within the capacitor, and so greatly influences the severity of these effects. And, since each manufacturer has a different recipe for their ceramic and for determining the number of plates, the effects will vary from manufacture to manufacturer. This means in critical applications you’ll need to carefully test capacitors from second sources.

For example, a 6.3V 100nF X7R capacitor is actually about 80nF if it’s used to decouple a 3.3V power supply, but that’s much better than the 20nF value of a 100nF 6.3V Y5V dcap. Increasing the temperature reduces the capacitance further (especially for the Y5V).

The rule I use is never to operate an X7R type capacitor at more than 75% of its rated working voltage. This holds for timing and for bypass (decoupling) applications. If for some reason Y5V or ZU5 capacitors must be used, never use them at more than 50% of their working voltage. Limiting them to voltages no higher than about 25% of the working voltage spec is even better. Incidentally, I never use them in timing or op-amp applications or to set the loop response in PLL circuits.

The bottom line is to understand types and ratings of the dcaps used in your design, and always account for the effects of voltage and temperature when modeling and simulating your power distribution network.

Several years ago I was doing a “walk through” of a client’s layout database. This is where I use a CAD viewer to look at the database (either the Gerber files or, if a custom tool is used, the layer files created by that tool). My client had electronically checked and simulated the database with one of the SI tools on the market, and the tool had declared the layout clean. Good to go. Ready for fab.

NOT!

My client’s engineering department was annoyed (skeptical, in fact) that I wanted to visually inspect each layer in the database because they were under some serious time pressure. The pricy SI tool which management agreed to buy (and their engineers used on the database) had declared the board ready, and because the project was late, just about everyone wanted the board in the lab now, if not sooner. Except maybe the diagnostic engineer who was behind schedule in developing test patterns for DVT, and who was, I think, secretly hoping we’d find a killer problem to hold up fab for a couple of weeks. But, because of my history with some of the folks at the firm, management reluctantly gave me one day to wonder through the database.

It didn’t take that long. Within about 2 hours a half a dozen abnormalities needing to be corrected had poped out. The diag engineer was thrilled (management was not).

I’ll post more on this in the future, but the take home message is that SI tools are wonderful, and necessary. In fact, in many instances SI tools are absolutely vital to getting a product out the door on time with minimum hardware debug. Just don’t let the tools get in the way of using your brain. As an SI engineer, or design engineer doing SI work, you understand context and can see the big picture far better than any tool.

Don’t let the report generated by a nice looking GUI fool you into thinking that the tool is expert. It probably isn’t. And, be absolutely sure to include enough time in your layout/fab schedule to do a walk through.