Thierauf Design & Consulting: Signal Integrity Design, Analysis & Training

Those visiting the Artech House booth at EDICON in Boston last week heard about the upcoming second edition of “High-Speed Circuit Board Signal Integrity”.

The 1st edition has been very popular with signal integrity engineers, test engineers and chip I/O designers responsible for high-performance signaling. But, a lot has changed in the 12 years since it first came out, and an update is in order.

While I was at it I decided to add new material so the book will also appeal to those engineers (and engineering students) needing to know about signal integrity, but who aren’t SI specialists.

For instance, the 2ed edition has a new chapter covering reflections and terminations, and the original discussion on transmission line losses has been improved. The original capacitor chapter has a lot of new material, and the discussions on return paths, decoupling and power integrity have been rewritten and expanded. S-Parameters (including differential S-Prams) are introduced and discussed for the first time.

Likewise, a new chapter discussing signal integrity pitfalls and layout techniques has been added. Some of this was scattered throughout the 1st edition but for the 2ed edition I’ve gathered it all into one chapter and added new material.

The matrix math that appeared throughout the 1st edition has been condensed and moved to the S-Pram chapter. This makes it easy for the reader to skip that level of math if they wish.

I’m guessing the book will be out sometime during the first half of 2017. I’ll post more once the publication schedule firms up.

You can contact me here if you have questions or would like to know more.