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Last Updated: 17 May 2012

One of the most common capacitor related questions I get from clients and readers regards the way ceramic capacitors are classified.

As I've noted elsewhere, Class II ceramic dielectrics (which are used to create most ceramic decoupling capacitors, such as X7R types) are made with materials that cause the capacitance to change with temperature and bias voltage. A three character identification scheme is used to describe these effects: The 1st and 2ed characters indicate the temperature span, and the 3ed shows by how much the capacitance can change over that range. For instance, the capacitance of the popular X7R type capacitor can change by +/- 15% (indicated by the "R") when operating from -55C (indicated by the "X") to +125C (indicated by the "7"). This change is in addition to the tolerance of the capacitor, which is measured at 25C (or sometimes 20C) and low bias voltage. Operating an X7R at 50% of its working voltage rating can result in the capacitance being reduced by nearly 20%, while the capacitance can be reduced by as much as 80% for other Class II dielectrics. The identification code doesn't directly show the way voltage changes the capacitance, but in general the "X" series is the least affected, followed by the "Y" and then the "Z" series. Manufacturer's literature sometimes shows this, and it's described in detail in chapter 10 of High-Speed Circuit Board Signal Integrity. Incidentally, a Class I dielectric (such as a C0G) should be used in those situations where the capacitance must not change with bias, such as integrators, PLL's and timing circuits.

Here's what each of the most common character codes mean for Class II dielectrics (Class I dielectrics such as C0G have their own, very different, code):

X = -55C              5 = +85C              R = +/- 15%

Y = -30C               6 = +105C            U = +22%, - 56%

Z = +10C               7 = +125C           V = +22%, -82%

One more note on Class II ceramic capacitors: remember the capacitance falls as they age, even when the circuit is not powered up. The "X" series show the least amount of aging (typically under 2.5% per decade hour), while the "Z" series the most (as much as 7% in reduction of capacitance per decade hour). But that's for another post.

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Last Updated: 17 May 2012

If you need a 3-D field solver, you might want to give Simbeor (http://www.simberian.com/) a try. This year it again won the Design Con Design Vision Award (it was the 2010 winner, too).

A big plus for me is that Simbeor results have been verified against measurement of actual hardware (you can get details on this from the Siberian website).

Some 3-D solvers can be very difficult to properly use, especially if you don't build models with them daily. The special tricks required to correctly assign ports or to set boundary conditions are easy to forget unless you use the tool enough to become truly expert.

In contrast, I've found it easy to build 3D transmission line and via models in Simbeor, even when I haven't used it for a while. The tutorials are excellent, and the website has a very nice collection of technically useful white papers (several of which I reference in "Understanding Signal Integrity").

This is a great tool for designing serial channels, designing vias, and analyzing the electrical behavior of interconnect (including, but not only, very high-performance interconnect). The website is worth checking out: It's a good resource for those wishing to learn about the electrical characteristics of high-performance serial signaling.

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Last Updated: 17 May 2012

In part 1 (which you can read here) I described the benefits of visually inspecting the layout database for signal integrity problems. In that true story a large SI team had run a fancy SI analysis tool on the database for their very complex circuit board and had found nothing amiss.

However, a quick walkthrough uncovered two pages of things needing further investigation. The following from that list were fatal.

1. Serpentine trace used to add delay in a memory system was improperly designed and had crosstalk excessive enough to cause ‘laddering’. The SI CAD tool noticed the serpentine and faithfully added the delays from each segment to come up with a total, but it didn’t account for the way in which crosstalk would have reduced the total delay. In fact, it proudly reported the (incorrect) delay to 3 decimal places!
2. The SI tool didn’t report that dcaps were sharing vias with other devices (in one case a clock driver). This had a huge potential to create data dependent switching noise that could wreak havoc with the clock system.
3. Terminating resistors for a very wide memory bus picked up Vtt (the termination voltage) from a very small island carved out of a power plane deep within the stackup. The voltage regulator feeding it was located a distance away, and was connected by a wide microstrip and a few vias. Because the island was deep in the stackup the long visas necessary to connect the regulator (and the dcap) to the island, and the long vias necessary to connect the resistors to Vtt were very inductive. A better solution (which was eventually implemented on a later spin of the board) was to move the island to the surface on the same side of the board where the termination resistors were located. This eliminated all of the vias and significantly improved signal quality. The SI tool had no understanding of this: it was happy because the voltage regulator was connected to a Vtt node, to which the termination resistors were connected.
4. High-speed diff-pairs were run very near holes in the circuit board where screws attached the board   to a carrier. In some cases the diff-pairs ran alongside a series of these holes, but in one astonishing case a diff-pair was split such that one hole was placed in between the two traces forming the diff pair. A sketch of this type of problem appears in Figure 13.13 of “Understanding Signal Integrity” (but that diagram shows the discontinuity as a via and antipad rather than a bolt hole).
5. The final one was perhaps the most subtle. A very wide high-speed memory bus was run as dual stripline. The layout designer had properly kept all the memory signals on the lower layer of the dual stripline, and had routed slow speed miscellaneous signals (including reset) on the upper dual stripline layer. This would have been fine provided those signals were not routed the same direction as the signals in the lower layer. Here is where multiple errors simultaneously came together to break the design. The first mistake was when the SI engineer specified that the reset signal was to be kept “as short as possible” (an instruction often given to layout designers but which really has no meaning). Faithfully following orders, the layout designer ran the reset trace diagonally across the board (it ended up as 18 inches [46cm]), since this gave a shorter length than a Manhattan route (nearly 30 inches [75cm]). That was the second mistake since the routing caused the trace to cut across (and so, pick up coupling from) every signal in the memory system and many other signals as well. Which leads us to mistake three: The SI engineer ran a simple TLINE simulation using the 18 inches from the length report which showed that the termination he had selected was adequate. Unfortunately his simulation didn’t include coupling from the other signals and so ignored crosstalk. The SI tool didn’t pick up on this because it was told to only analyze the memory subsystem. Since the coupling from the reset signal to each individual memory trace was small, it didn’t raise a flag. However, the total coupling from all of the memory traces TO the reset signal was very high. High enough in fact to cause reset to glitch when many of the memory traces simultaneously changed state in the same direction. Here the SI engineer was blinded by the impressive looking report generated by the tool.

The moral: always verify the cad tool results. Don’t just blindly accept the results and assume the tool is doing what you actually want.

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Last Updated: 17 May 2012

If you are looking for a version of SPICE to perform some basic circuit analysis, including elementary signal integrity analysis, you might consider using one of the free versions provided by the various major semiconductor vendors.

As I describe at the end of this note, just be careful how you use the transmission line models, and you’re limited in the types of I/O models you’ll be able to simulate because these simulators don’t support IBIS or encrypted transistor models. You’ll need to use a “full blown” version of SPICE to perform professional quality SI simulations.

Arguably the best known of the free Windows versions of SPICE is LTSPICE, which Linear Technology has made available for some time now. LTSPICE IV can be downloaded from the Linear Tech website here:

http://www.linear.com/designtools/software/gclid=CNaN2ZmwwqcCFYHc4AodAjnhAg#LTspice

The download includes models for a large selection of LTs product line, but models for a nice collection of transistors and diodes often used in switching power supply applications are also included. Models for other devices (such as transistors or diodes not included in the original library) can be easily added by the user.

Texas Instruments offers TINA (from Design Soft). It, too, is free and runs under Windows. It can be down loaded from the TI website:

http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html

TINA includes models of many TI analog components, and also for various transistors and diodes. Macro models for a number of logic devices and some analog components are provided, too. For instance, they have a macro for the 555 timer.

Analog Devices has just announced a new version of National Instruments Multisim for the evaluation of ADI’s components. The download is free, runs under Windows, but is limited to 50 components. The download license agreement precludes student use. Download the ADI version of Multisim from the ADI site:

https://lumen.ni.com/nicif/us/evalmultisimadi/content.xhtml

This version of Multisim includes models for many components in ADI’s portfolio, and some transistors and diodes, too.

LTSPICE and Multisim include single conductor lossless and single frequency lossy transmission line models. These TLINES are useful in predicting the severity of reflections, and the effects of terminations. However, since the TLINEs are single conductor, crosstalk can’t be measured, but because the model includes the TLINE reference terminals, coupling over a noisy ground plane can be simulated.

The lossy TLINES include series resistance and (shunt) conductance terms, which are used to account for conductor and dielectric losses. But, because the values don’t change with frequency, these lossy TLINEs are only good for modeling losses at the one specific frequency for which the resistance and conductance are valid. So you shouldn’t expect these TLINEs to properly account for losses in pulse circuits, but they give good results when a single frequency sinusoid is transmitted.