Thierauf Design & Consulting: Signal Integrity Design, Analysis & Training

If you are looking for a version of SPICE to perform some basic circuit analysis, including elementary signal integrity analysis, you might consider using one of the free versions provided by the various major semiconductor vendors.

As I describe at the end of this note, just be careful how you use the transmission line models, and you’re limited in the types of I/O models you’ll be able to simulate because these simulators don’t support IBIS or encrypted transistor models. You’ll need to use a “full blown” version of SPICE to perform professional quality SI simulations.

Arguably the best known of the free Windows versions of SPICE is LTSPICE, which Linear Technology has made available for some time now. LTSPICE IV can be downloaded from the Linear Tech website here:

The download includes models for a large selection of LTs product line, but models for a nice collection of transistors and diodes often used in switching power supply applications are also included. Models for other devices (such as transistors or diodes not included in the original library) can be easily added by the user.

Texas Instruments offers TINA (from Design Soft). It, too, is free and runs under Windows. It can be down loaded from the TI website:

TINA includes models of many TI analog components, and also for various transistors and diodes. Macro models for a number of logic devices and some analog components are provided, too. For instance, they have a macro for the 555 timer.

Analog Devices has just announced a new version of National Instruments Multisim for the evaluation of ADI’s components. The download is free, runs under Windows, but is limited to 50 components. The download license agreement precludes student use. Download the ADI version of Multisim from the ADI site:

This version of Multisim includes models for many components in ADI’s portfolio, and some transistors and diodes, too.

LTSPICE and Multisim include single conductor lossless and single frequency lossy transmission line models. These TLINES are useful in predicting the severity of reflections, and the effects of terminations. However, since the TLINEs are single conductor, crosstalk can’t be measured, but because the model includes the TLINE reference terminals, coupling over a noisy ground plane can be simulated.

The lossy TLINES include series resistance and (shunt) conductance terms, which are used to account for conductor and dielectric losses. But, because the values don’t change with frequency, these lossy TLINEs are only good for modeling losses at the one specific frequency for which the resistance and conductance are valid. So you shouldn’t expect these TLINEs to properly account for losses in pulse circuits, but they give good results when a single frequency sinusoid is transmitted.

Now that you’ve picked the values for your ceramic decoupling capacitors, how do you decide on the working voltage rating? This is an important factor because unless you derate the dcap working voltage there’ll be less capacitance in the design than you had intended.

It turns out that the actual capacitance value of class II ceramic capacitors such as a 0.1uF X7R or Y5V dcap is influenced by the intensity of the electric field within the capacitor. Class II is the ceramic class from which almost all capacitors used for decoupling on commercial printed circuit boards comes from. Even when the power supply voltage in a circuit is low, the small size of modern SMT capacitors means the electric fields within the dcap can be quite high. And, the fields will be even higher in those capacitors constructed of many plates which are separated by a thin smear of dielectric (this is one of the techniques used by vendors get high values of capacitance in such small packages).

I’ve written extensively on the makeup and characteristics of Class I and Class II ceramic capacitors, but manufacturer’s datasheets and websites also have lots of great information. Some vendors offer software that you can use showing how their capacitors are affected by temperature and voltage. One of my favorites is SpiCap3.0 from AVX, which you can check out here.

If you drill into this you’ll see how strongly the capacitance of class II ceramic capacitors is reduced by voltage. The best way is to look at this is to plot the capacitance as a percentage of the specified working voltage. For instance, you’ll find that, depending on the body style, capacitance value and manufacturer, when exposed to voltages of 50% or more of the working voltage rating, the capacitance of an X7R can be reduced by as much as 20% over its datasheet value. The capacitance can be as low as an astonishing 20% of the specified value for an Y5V, and can be close to that for a Z5U.

The amount of capacitance and the body style determine the number and thickness of the plates within the capacitor, and so greatly influences the severity of these effects. And, since each manufacturer has a different recipe for their ceramic and for determining the number of plates, the effects will vary from manufacture to manufacturer. This means in critical applications you’ll need to carefully test capacitors from second sources.

For example, a 6.3V 100nF X7R capacitor is actually about 80nF if it’s used to decouple a 3.3V power supply, but that’s much better than the 20nF value of a 100nF 6.3V Y5V dcap. Increasing the temperature reduces the capacitance further (especially for the Y5V).

The rule I use is never to operate an X7R type capacitor at more than 75% of its rated working voltage. This holds for timing and for bypass (decoupling) applications. If for some reason Y5V or ZU5 capacitors must be used, never use them at more than 50% of their working voltage. Limiting them to voltages no higher than about 25% of the working voltage spec is even better. Incidentally, I never use them in timing or op-amp applications or to set the loop response in PLL circuits.

The bottom line is to understand types and ratings of the dcaps used in your design, and always account for the effects of voltage and temperature when modeling and simulating your power distribution network.

Several years ago I was doing a “walk through” of a client’s layout database. This is where I use a CAD viewer to look at the database (either the Gerber files or, if a custom tool is used, the layer files created by that tool). My client had electronically checked and simulated the database with one of the SI tools on the market, and the tool had declared the layout clean. Good to go. Ready for fab.


My client’s engineering department was annoyed (skeptical, in fact) that I wanted to visually inspect each layer in the database because they were under some serious time pressure. The pricy SI tool which management agreed to buy (and their engineers used on the database) had declared the board ready, and because the project was late, just about everyone wanted the board in the lab now, if not sooner. Except maybe the diagnostic engineer who was behind schedule in developing test patterns for DVT, and who was, I think, secretly hoping we’d find a killer problem to hold up fab for a couple of weeks. But, because of my history with some of the folks at the firm, management reluctantly gave me one day to wonder through the database.

It didn’t take that long. Within about 2 hours a half a dozen abnormalities needing to be corrected had poped out. The diag engineer was thrilled (management was not).

I’ll post more on this in the future, but the take home message is that SI tools are wonderful, and necessary. In fact, in many instances SI tools are absolutely vital to getting a product out the door on time with minimum hardware debug. Just don’t let the tools get in the way of using your brain. As an SI engineer, or design engineer doing SI work, you understand context and can see the big picture far better than any tool.

Don’t let the report generated by a nice looking GUI fool you into thinking that the tool is expert. It probably isn’t. And, be absolutely sure to include enough time in your layout/fab schedule to do a walk through.

My latest book (“Understanding Signal Integrity”) has been out for a few months now and I'm pleased to see how well it's being received by academic libraries throughout the world.

I think a big attraction for those libraries is the student problem sets appearing at the end of many chapters. Answers are provided for all of the problems, and I tried to make them as real world as I could. In many cases you can use them as templates to solve similar problems in your design. The answers are detailed (they take something like 50 pages in WORD format, which would end up being many times that number in a printed book). Rather than cutting out the details the Publisher and I agreed to post them in their entirety on their web site. You can down load a copy of the answers here.