Thierauf Design & Consulting: Signal Integrity Design, Analysis & Training

Those visiting the Artech House booth at EDICON in Boston last week heard about the upcoming second edition of “High-Speed Circuit Board Signal Integrity”.

The 1st edition has been very popular with signal integrity engineers, test engineers and chip I/O designers responsible for high-performance signaling. But, a lot has changed in the 12 years since it first came out, and an update is in order.

While I was at it I decided to add new material so the book will also appeal to those engineers (and engineering students) needing to know about signal integrity, but who aren’t SI specialists.

For instance, the 2ed edition has a new chapter covering reflections and terminations, and the original discussion on transmission line losses has been improved. The original capacitor chapter has a lot of new material, and the discussions on return paths, decoupling and power integrity have been rewritten and expanded. S-Parameters (including differential S-Prams) are introduced and discussed for the first time.

Likewise, a new chapter discussing signal integrity pitfalls and layout techniques has been added. Some of this was scattered throughout the 1st edition but for the 2ed edition I’ve gathered it all into one chapter and added new material.

The matrix math that appeared throughout the 1st edition has been condensed and moved to the S-Pram chapter. This makes it easy for the reader to skip that level of math if they wish.

I’m guessing the book will be out sometime during the first half of 2017. I’ll post more once the publication schedule firms up.

You can contact me here if you have questions or would like to know more.


People have been asking how Figure C.7 in Understanding Signal Integrity: A Laboratory Manual was created. This graphic shows the difference between using the ground spring on the end of an oscilloscope probe verses using a 6” (15cm) long wire.

You can see in Figure C.7 (on the right, reproduced from the text) that with the wire lead the probe doesn’t act as you’d expect from theory (which was shown in Figure C.6). Some frequencies are displayed by the oscilloscope with larger amplitudes than the actual measurement (the Y axis 100% mark), but others are displayed with less than what was actually present. Pulses (which are made from many harmonic frequencies) will be distorted, and their shape and the amount of ringing will change as the ground lead is repositioned or changed in length.Capture22.JPG

So, how was the plot taken, and how can you measure the characteristics of your own probe?

I used the tracking generator from my RF spectrum analyzer as a source because I know its output is flat across the frequency range I wanted to measure. You cans also use a sine wave generator provided you know its output is flat (the amplitude doesn’t change as you adjust the frequency).


Because you want to determine the response when your probe is connected to your oscilloscope, the best way to make the measurement is to connect the probe to your oscilloscope and attach the probe tip and ground lead to the generator output. Don’t use the spectrum analyzer input because its frequency response isn’t the same as the frequency response of your oscilloscope. I set the tracking generator output amplitude to a convenient value and measured the amplitude on the scope when I changed the frequency in 10MHz increments from 1MHz to 300MHz. The results are displayed in Figure C.7. With this setup you can see how the frequency response changes as the ground wire is repositioned, or when you make it longer or shorter.

All of the printing production problems have been worked out, and the lab manual is now available!

Click here for a PDF of the Table of Contents, and sample text from Chapter 5.

Order your copy by clicking here.

thierauf lab manual coverA sample chapter from Introduction to Signal Integrity: A Laboratory Manual is available.

Click here to download the PDF (you must be able to read PDFs in Version 9 or later). The file contains the Table of Contents, the entire Preface and part of Chapter 5 (but some graphics and text have been removed). Note that the print quality of the actual manual is much better than that presented in the sample chapter.





Table of Contents

Chapter 1 Signal Integrity Background Material
Chapter 2 Transmission Line Fundamentals
Chapter 3 Laboratory Exercises: Impedance and Delay
Chapter 4 Overview of Reflections and Terminations
Chapter 5 Laboratory Exercises: Reflections and Terminations
Chapter 6 Fundamentals of Crosstalk
Chapter 7 Laboratory Exercises: Measuring Crosstalk
Appendix A. Test Setup Build Notes
Appendix B. Selecting and Preparing the Cable
Appendix C. Oscilloscope Probing Techniques

In a previous blog I mentioned how the lossy transmission line model included in some versions of SPICE won’t properly simulate pulses. There’s been a lot of interest in this since that posting went live, especially with regards to finding the conductance loss and in using lossy TLINES in the free or reduced cost SPICE simulators.

Some SPICE based circuit simulators include the LTRA (Lossy TRAnsmission line) model (the “O” element). It simulates TLINE behavior (including loss) for one signal conductor at one frequency. That’s why it works well for single frequency waves (such as low distortion sine waves), but it doesn’t properly calculate losses for pulses, which are made of many frequencies (harmonics). And, since the “O” line only models one signal, it can’t be used to determine crosstalk or to simulate differential pairs.

With these caveats in mind, here’s how to calculate the parameters for a 50 ohm, 5-mil wide, half-ounce thick stripline on FR4. Some of you may recognize the raw data as coming from problem 7.12 of “Understanding Signal Integrity”.

The model requires we know the trace length (LEN), along with its capacitance (C), inductance (L), resistance (R), and conductance (G) all determined at the frequency of interest. The resistance models signal loss of the conductor metal, and the conductance models the dielectric loss. Both of these get larger as frequency increases, but the model uses the same values for all frequencies.

We’ll use 350MHz (the same frequency used in problem 7.12). R, L and C are found at that frequency with a field solver, or by using the graphs or formulas in the book, to be (per inch length):

C = 3.5p



We recall from the text that R is the AC resistance of the trace and its return path at 350MHz. It’s not the DC value.

All we need to do now is to calculate G to complete the model. As I show in the text and in problem 7.11, this is easily done once we know the capacitance and the circuit boards loss tangent (which we’ll take to be 0.02 for FR4).

G = 6.28 x f x C x LT = 6.28 x 350MHz x 3.5pF x 0.02 = 154uS/inch

The loss is given in Siemens per unit length (using the same units as for the capacitance). For a 15 inch long line at 350MHz the final model becomes:







As I show in the book, these need to be scaled when using the “W” line model. But that’s for another post.

One of the most common capacitor related questions I get from clients and readers regards the way ceramic capacitors are classified.

As I've noted elsewhere, Class II ceramic dielectrics (which are used to create most ceramic decoupling capacitors, such as X7R types) are made with materials that cause the capacitance to change with temperature and bias voltage. A three character identification scheme is used to describe these effects: The 1st and 2ed characters indicate the temperature span, and the 3ed shows by how much the capacitance can change over that range. For instance, the capacitance of the popular X7R type capacitor can change by +/- 15% (indicated by the "R") when operating from -55C (indicated by the "X") to +125C (indicated by the "7"). This change is in addition to the tolerance of the capacitor, which is measured at 25C (or sometimes 20C) and low bias voltage. Operating an X7R at 50% of its working voltage rating can result in the capacitance being reduced by nearly 20%, while the capacitance can be reduced by as much as 80% for other Class II dielectrics. The identification code doesn't directly show the way voltage changes the capacitance, but in general the "X" series is the least affected, followed by the "Y" and then the "Z" series. Manufacturer's literature sometimes shows this, and it's described in detail in chapter 10 of High-Speed Circuit Board Signal Integrity. Incidentally, a Class I dielectric (such as a C0G) should be used in those situations where the capacitance must not change with bias, such as integrators, PLL's and timing circuits.

Here's what each of the most common character codes mean for Class II dielectrics (Class I dielectrics such as C0G have their own, very different, code):

X = -55C              5 = +85C              R = +/- 15%

Y = -30C               6 = +105C            U = +22%, - 56%

Z = +10C               7 = +125C           V = +22%, -82%


One more note on Class II ceramic capacitors: remember the capacitance falls as they age, even when the circuit is not powered up. The "X" series show the least amount of aging (typically under 2.5% per decade hour), while the "Z" series the most (as much as 7% in reduction of capacitance per decade hour). But that's for another post.

If you need a 3-D field solver, you might want to give Simbeor ( a try. This year it again won the Design Con Design Vision Award (it was the 2010 winner, too).

A big plus for me is that Simbeor results have been verified against measurement of actual hardware (you can get details on this from the Siberian website).

Some 3-D solvers can be very difficult to properly use, especially if you don't build models with them daily. The special tricks required to correctly assign ports or to set boundary conditions are easy to forget unless you use the tool enough to become truly expert.

In contrast, I've found it easy to build 3D transmission line and via models in Simbeor, even when I haven't used it for a while. The tutorials are excellent, and the website has a very nice collection of technically useful white papers (several of which I reference in "Understanding Signal Integrity").

This is a great tool for designing serial channels, designing vias, and analyzing the electrical behavior of interconnect (including, but not only, very high-performance interconnect). The website is worth checking out: It's a good resource for those wishing to learn about the electrical characteristics of high-performance serial signaling.

In part 1 (which you can read here) I described the benefits of visually inspecting the layout database for signal integrity problems. In that true story a large SI team had run a fancy SI analysis tool on the database for their very complex circuit board and had found nothing amiss.

However, a quick walkthrough uncovered two pages of things needing further investigation. The following from that list were fatal.

  1. Serpentine trace used to add delay in a memory system was improperly designed and had crosstalk excessive enough to cause ‘laddering’. The SI CAD tool noticed the serpentine and faithfully added the delays from each segment to come up with a total, but it didn’t account for the way in which crosstalk would have reduced the total delay. In fact, it proudly reported the (incorrect) delay to 3 decimal places!
  2. The SI tool didn’t report that dcaps were sharing vias with other devices (in one case a clock driver). This had a huge potential to create data dependent switching noise that could wreak havoc with the clock system.
  3. Terminating resistors for a very wide memory bus picked up Vtt (the termination voltage) from a very small island carved out of a power plane deep within the stackup. The voltage regulator feeding it was located a distance away, and was connected by a wide microstrip and a few vias. Because the island was deep in the stackup the long visas necessary to connect the regulator (and the dcap) to the island, and the long vias necessary to connect the resistors to Vtt were very inductive. A better solution (which was eventually implemented on a later spin of the board) was to move the island to the surface on the same side of the board where the termination resistors were located. This eliminated all of the vias and significantly improved signal quality. The SI tool had no understanding of this: it was happy because the voltage regulator was connected to a Vtt node, to which the termination resistors were connected.
  4. High-speed diff-pairs were run very near holes in the circuit board where screws attached the board   to a carrier. In some cases the diff-pairs ran alongside a series of these holes, but in one astonishing case a diff-pair was split such that one hole was placed in between the two traces forming the diff pair. A sketch of this type of problem appears in Figure 13.13 of “Understanding Signal Integrity” (but that diagram shows the discontinuity as a via and antipad rather than a bolt hole).
  5. The final one was perhaps the most subtle. A very wide high-speed memory bus was run as dual stripline. The layout designer had properly kept all the memory signals on the lower layer of the dual stripline, and had routed slow speed miscellaneous signals (including reset) on the upper dual stripline layer. This would have been fine provided those signals were not routed the same direction as the signals in the lower layer. Here is where multiple errors simultaneously came together to break the design. The first mistake was when the SI engineer specified that the reset signal was to be kept “as short as possible” (an instruction often given to layout designers but which really has no meaning). Faithfully following orders, the layout designer ran the reset trace diagonally across the board (it ended up as 18 inches [46cm]), since this gave a shorter length than a Manhattan route (nearly 30 inches [75cm]). That was the second mistake since the routing caused the trace to cut across (and so, pick up coupling from) every signal in the memory system and many other signals as well. Which leads us to mistake three: The SI engineer ran a simple TLINE simulation using the 18 inches from the length report which showed that the termination he had selected was adequate. Unfortunately his simulation didn’t include coupling from the other signals and so ignored crosstalk. The SI tool didn’t pick up on this because it was told to only analyze the memory subsystem. Since the coupling from the reset signal to each individual memory trace was small, it didn’t raise a flag. However, the total coupling from all of the memory traces TO the reset signal was very high. High enough in fact to cause reset to glitch when many of the memory traces simultaneously changed state in the same direction. Here the SI engineer was blinded by the impressive looking report generated by the tool.

The moral: always verify the cad tool results. Don’t just blindly accept the results and assume the tool is doing what you actually want.